20220414: 
1. Update NM1530.h
/*******************************************************************************
Error:  #define EPWM_PNPC_PNP0_Pos 1 
Correct:#define EPWM_PNPC_PNP0_Pos 0  
*******************************************************************************/


2. Update qei.h
/*******************************************************************************
* Update on 20220406 by Brian
* Error:	#define QEI_SET_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL = (u32Type))
* Correct:#define QEI_SET_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL |= (u32Type))
* Error:  #define QEI_GET_DIR(qei)    (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
* Correct:#define QEI_GET_DIR(qei)    (((qei)->STATUS & (QEI_STATUS_DIRSTS_Msk))?1:0)
*******************************************************************************/

3. Update clk.h
/*******************************************************************************
#elif (__HXT == 16000000)			//for 16MHz HXT
#define CLK_PLLCON_72MHz_HXT   (CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR(2) | CLK_PLLCON_NF( 18) | CLK_PLLCON_NO_2) /*!< Predefined PLLCON setting for 72MHz PLL output with HXT */
*******************************************************************************/


4. Update clk.c
/*******************************************************************************
     W@ "uint32_t CLK_SetCoreClock(uint32_t u32Hclk)" PLL freq]144MHz
     令72MHz
        A1. //u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, (u32Hclk << 1));	//lBSP codePLL freq]144MHz
				A2. u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, (u32Hclk));					//Brian: ק令PLL freq = 72MHz in 20220324
        
        B1. //CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));			//lBSP code HCLK_freq=PLL_freq/2
		    B2. CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));				//Brian: ק令 HCLK_freq=PLL_freq/1 in 20220324
*******************************************************************************/        
